IM2G04D2DBBG-25

Intelligent Memory
822-IM2G04D2DBBG-25
IM2G04D2DBBG-25

Mfr.:

Description:
DRAM DDR2 2Gb, 1.8V, 512Mx4, 400MHz (800Mbps), 0C to +95C, FBGA-60

Datasheet:
ECAD Model:
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Learn more about Intelligent Memory IM2G04D2DBBG-25

Availability

Stock:
0

You can still purchase this product for backorder.

Factory Lead-Time:
26 Weeks Estimated factory production time.
Long lead time reported on this product.
Minimum: 1   Multiples: 1
Unit Price:
$-.--
Ext. Price:
$-.--
Est. Tariff:

Pricing (CAD)

Qty. Unit Price
Ext. Price
$43.26 $43.26
$40.05 $400.50
$38.77 $969.25
$37.82 $1,891.00

Product Attribute Attribute Value Select Attribute
Intelligent Memory
Product Category: DRAM
RoHS:  
SDRAM - DDR2
2 Gbit
4 bit
400 MHz
FBGA-60
512 M x 4
400 ps
1.7 V
1.9 V
0 C
+ 95 C
IM2G04D2
Tray
Brand: Intelligent Memory
Country of Assembly: Not Available
Country of Diffusion: Not Available
Country of Origin: CN
Moisture Sensitive: Yes
Mounting Style: SMD/SMT
Product Type: DRAM
Factory Pack Quantity: 264
Subcategory: Memory & Data Storage
Supply Current - Max: 58 mA
Unit Weight: 179 mg
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Attributes selected: 0

Datasheet

CAHTS:
8542320020
USHTS:
8542320036
MXHTS:
8542320299
ECCN:
EAR99

Dynamic Random Access Memory (DRAM)

Intelligent Memory Dynamic Random Access Memory (DRAM) includes a full range of JEDEC-compliant DRAMs and ECC DRAMs (SDRAM, DDR, DDR2, DDR3, DDR4, LPDDR4). From an application's point of view, these components work like a monolithic device. The DRAM devices allow for maximum levels of memory density without altering existing board layouts or designs.

Double Data Rate 2 (DDR2) SDRAM

Intelligent Memory Double Data Rate (DDR2) Synchronous DRAM (SDRAM) are eight-bank devices that achieve high-speed data transfer rates. Interleaving the eight memory banks allows random access operations faster than standard DRAMs. A chip architecture prefetches multiple bits and then synchronizes the output data to a system clock. All control, address, and circuits are synchronized with the positive edge of an externally supplied clock. In a source-synchronous manner, I/Os are synchronized with a pair of bidirectional strobes. A sequential, gapless data rate is possible depending on the device's burst length, CAS latency, and speed grade.

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